The most advanced computer processor manufacturers are in the middle of the first major change in device architecture in a decade, from finFETs to nanosheets. Another decade should see another fundamental change, with nanosheet devices stacked on top of each other to form complementary field-effect transistors (CFETs) capable of cutting the size of some circuits in half. But the final step is likely to be tough, experts say. An intermediate transistor called a fork sheet can compress circuits without much effort.
“The forksheet idea came about as a result of exploring the limitations of nanosheet architecture,” says Julien Rickert, vice president of logic technology at Imec. The main feature of the nanosheet is its horizontal stacks of silicon ribbons surrounded by a current-controlling gate. Although the production of nanosheets has only recently begun, experts have already been looking for their limits many years ago. Imek was tasked with figuring out “at what point the nanosheet will start to break down,” he says.
Rycart’s team found that one of the main limitations in the nanosheet-based logic reduction path is maintaining the separation between the two types of transistors that make up the CMOS logic. Two types – NMOS and PMOS – must support a certain distance in order to limit the capacity that reduces the performance and power consumption of devices. “The fork is a way to get around this limitation,” Reikert says.
Instead of individual nanosheet devices, the fork-sheet circuit builds them in pairs on either side of the dielectric wall. (No, it doesn’t really look like a plug.) The wall allows devices to be placed closer together without causing capacity issues, says Naoto Horiguchi, director of CMOS technology at Imec. Designers could use the extra space to make logic cells smaller, he says, or they could use the extra space to build transistors with wider sheets, which would result in better performance.
Advanced transistors are already moving from the fin field-effect transistor (FinFET) architecture to nanosheets. The end goal is to place two devices on top of each other in a CFET configuration. Forklist may be an intermediate step along the way.imek
“CFET is likely the final CMOS architecture,” Horiguchi says of the device, which Imec estimates will be ready for production around 2032. But he adds that “CFET integration is very difficult.” Forksheet reuses most of the nanosheet production steps, potentially simplifying the job, he says. Imec predicts that it could be ready around 2028.
However, there are still many obstacles to be overcome. “It’s more difficult than originally thought,” says Horiguchi. From a production point of view, a dielectric wall is a bit of a headache. There are several types of dielectrics used in advanced CMOS and several steps that involve removing it. Making fork sheets means etching those others without accidentally attacking the wall. According to Horiguchi, the question of what types of transistors should be placed on both sides of the wall remains an open question. The original idea was to put a PMOS on one side and an NMOS on the other, but there may be advantages to putting the same type on both sides instead.
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