There was a time, decades actually, when all it took to make a better computer chip was smaller transistors and narrower interconnects. That time is long gone, and while transistors will continue to get smaller, it just doesn’t make sense to make them that way anymore. The only way to keep the exponential pace of computing going right now is with a scheme called System Technology Cooperative Optimization (STCO), researchers said at ITF World 2023 last week in Antwerp, Belgium. It is the ability to break down chips into their functional components, use optimal transistors and interconnect technologies for each function, and stitch them together to create a lower power consumption, more efficient whole.

“This brings us to a new paradigm for CMOS,” says Imec research and development manager Marie Garcia Bardon. CMOS 2.0, as the Belgian nanotechnology research organization calls it, is a complex vision. But it may be the most practical way forward, and some of it is already evident in today’s most advanced chips.

How did we get here

In a sense, the semiconductor industry was corrupted for decades prior to 2005, says Julien Rickert, vice president of research and development at Imec. During this time, chemists and device physicists were able to routinely produce smaller, lower power, and faster transistors that could be used for every function on a chip, leading to ever-increasing computing power. But soon after that, the wheels began to move away from this scheme. Device engineers could come up with great new transistors, but those transistors didn’t allow for better, smaller circuits like SRAM and standard logic cells that make up the bulk of processors. In response, chip manufacturers began to break down the barriers between standard cell design and transistor development. The new scheme, called Design Technology Cooperative Optimization (DTCO), has resulted in devices specifically designed to improve standard cells and memory.

But DTCO is not enough to keep computing running. The limitations of physics and economic realities conspire to put barriers to progress with the universal transistor. For example, physical limitations prevented the CMOS operating voltage from dropping below about 0.7V, which slowed down the rise in power consumption, explains Anabela Veloso, chief engineer at Imec. Switching to multi-core processors helped solve this problem for a while. Meanwhile, I/O limitations meant that it became more and more necessary to integrate the functions of multiple chips into the processor. Thus, in addition to a system on a chip (SoC) having multiple instances of processor cores, they also integrate networking, memory, and often specialized signal processing cores. Not only do these cores and features have different power and other needs, they also cannot be scaled down at the same rate. Even the CPU’s cache memory, SRAM, doesn’t shrink as fast as the CPU’s logic.

Joint optimization of system technologies

Getting things out of the dead end is not only a philosophical shift, but also a set of technologies. According to Rycart, STCO means considering the system-on-a-chip as a set of functions such as power supply, I/O, and cache memory. “When you start talking about features, you realize that SoC is not a homogeneous system, but just transistors and interconnects,” he says. “These are features optimized for different purposes.”

Ideally, you could build each feature using the most appropriate process technology for it. In practice, this basically means building each one on its own piece of silicon or chiplet. And then tie them together using technologies such as advanced 3D stacking so that all functions work as if they were on a single piece of silicon.

Examples of this kind of thinking are already present in advanced AI processors and accelerators. The Intel Ponte Vecchio High Performance Computing Accelerator (now called the Intel Data Center GPU Max) consists of 47 chiplets built using two different processes from Intel and TSMC. AMD already uses different technologies for I/O chips and compute chips in its processors, and recently began dedicating SRAM to high-level compute chip caches.

Imec’s roadmap for CMOS 2.0 goes even further. This requires further shrinking of transistors, moving power and possibly clocks under the CPU silicon, and ever tighter integration of 3D chips. “We can use these technologies to recognize different features, separate the SoC and re-integrate it to achieve maximum efficiency,” Reikert says.

For series of progressive letters, numbers and flow charts.Transistors will change shape in the coming decade, but so will the metal that connects them. Ultimately, transistors can be composite devices made up of 2D semiconductors instead of silicon. And power supply and other infrastructure can be located under the transistors.imek

Transistor scaling continued

Major chip manufacturers are already moving away from the FinFET transistors that have been used in computers and smartphones over the last decade to a new architecture called nanosheet transistors. [See “The Nanosheet Transistor is the Next Step in Moore’s Law”] Ultimately, two nanosheet transistors will be built on top of each other to form a complementary field-effect transistor, or CFET, which Velloso says “represents the maximum scaling of CMOS.” [See “3D-stacked CMOS Takes Moore’s Law to New Heights”]

As these devices shrink and change shape, one of the main goals is to reduce the size of standard logical cells. This is usually measured by “track height”, basically the number of metal connecting lines that can fit in the cell. Advanced FinFETs and early nanosheet devices are 6-track cells. Going to 5 tracks may require an intermediate design called a fork leaf that squeezes devices more closely without necessarily making them smaller. The CFET will then reduce the number of cells to 4 lanes or possibly less.

Four multi-colored blocks with arrows between them indicating progress.Advanced transistors are already moving from the fin field-effect transistor (FinFET) architecture to nanosheets. The end goal is to place two devices on top of each other in a CFET configuration. Forksheet can be an intermediate step along the way.imek

Chip makers will be able to create the thinner features needed for this advancement using next-generation ASML lithography for extreme ultraviolet, Imec says. This technology, called High Numerical Aperture EUV, is currently under development at ASML and Imec will be next in line. Increasing the numerical aperture (an optical term referring to the range of angles at which a system can collect light) results in more accurate images.

Rear power supply networks

The basic idea behind back-end power networks is to remove all interconnects that carry power—as opposed to data signals—above the silicon surface and place them below it. This should provide less power loss because the power supply interconnects can be larger and less stable. It also frees up space above the transistor layer for signal-carrying interconnects, possibly resulting in more compact designs. [See “Next-Gen Chips Will Be Powerd From Below”.]

In the future, even more could be moved to the back side of the silicon. For example, so-called global interconnects, which span (relatively) long distances for transmitting clocks and other signals, may be under the silicon. Or engineers can add active power delivery devices such as ESD protection diodes.

3D integration

There are several ways of 3D integration, but the most advanced to date are hybrid connection of wafers to wafers and crystals to wafers. [See “3 Ways 3D Chip Tech is Upending Computing”.] These two provide the highest interconnection density between two silicon dies. But this requires the two dies to be designed together so that their functions and connection points match, allowing them to operate as a single chip, says Ann Jourdain, chief technical staff member. Imec R&D is on track to create millions of 3D joints per square millimeter in the near future.

Going to CMOS 2.0

CMOS 2.0 takes disaggregation and heterogeneous integration to the extreme. Depending on which technologies make sense for particular applications, this can lead to a 3D system that includes layers of onboard memory, I/O and power infrastructure, high density logic, high drive current logic, and huge amounts of cache. memory.

Getting to this point will require not only technology development, but tools and training to determine which technologies will actually improve the system. As Bardon notes, smartphones, servers, machine learning accelerators, augmented and virtual reality systems have very different requirements and limitations. What makes sense for one may be a dead end for another.

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